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data sheet idt5t9304 revision a january 21, 2010 1 ?2010 integrated device technology, inc. lvds, 1:4 clock buffer terabuffer? idt5t9304 general description the idt5t9304 differential clock buffer has a user-selectable differential input to four lvds outputs. the fanout from a differential input to four lvds outputs reduces loading on the preceding driver and provides an efficient clock di stribution network. the idt5t9304 can act as a translator from a differential hstl, ehstl, lvepecl (2.5v), lvpecl (3.3v), cml, or lvds input to lvds outputs. a single-ended 3.3v / 2.5v lvttl inpu t can also be used to translate to lvds outputs. the redundant input capability allows for an asynchronous change-over from a primary clock source to a secondary clock source. selectable reference inputs are controlled by sel. the idt5t9304 outputs can be asyn chronously enabled/disabled. when disabled, the outputs will drive to the value selected by the gl pin. multiple power and grounds reduce noise. applications ? clock distribution features ? guaranteed low skew: 50ps (maximum) ? very low duty cycle distortion: 125ps (maximum) ? propagation delay: 1.75ns (maximum) ? up to 450mhz operation ? selectable inputs ? hot insertable and over-voltage tolerant inputs ? 3.3v/2.5v lvttl, hstl ehstl, lvepecl (2.5v), lvpecl (3.3v), cml or lvds input interface ? selectable differential inputs to four lvds outputs ? 2.5v v dd ? 0c to 70c ambient operating temperature ? available in standard (rohs 5) and lead-free (rohs 6) packages pin assignment idt5t9304 24-lead tssop 4.4mm x 7.8mm x 1.0mm package body g package top view 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 gnd gnd pd reserved v dd q1 q1 q2 q2 v dd sel g a2 a2 gnd v dd q3 q3 q4 q4 v dd gl a1 a1
idt5t9304 revision a january 21, 2010 2 ?2010 integrated device technology, inc. idt5t9304 data sheet 2.5v lvds, 1:4 clock buffer terabuffer? block diagram gl g pd a1 a1 a2 a2 sel output control output control output control output control q2 q2 q1 q1 q3 q3 q4 q4 1 0
idt5t9304 revision a january 21, 2010 3 ?2010 integrated device technology, inc. idt5t9304 data sheet 2.5v lvds, 1:4 clock buffer terabuffer? table 1. pin descriptions notes: 1. inputs are capable of translating the following interface standards: single-ended 3.3v and 2.5v lvttl levels differential hstl and ehstl levels differential lvepecl (2.5v) and lvpecl (3.3v) levels differential lvds levels differential cml levels 2. because the gate controls are asynchronous, runt pulses are po ssible. it is the user's responsibility to either time the gate control signals to minimize the possibility of runt pulses or be able to tolerate them in down stream circuitry. 3. it is recommended that the outputs be disabled before entering power-down mode. it is also recommended that the outputs remai n disabled until the device completes power-up after asserting pd . 4. the user must take precautions with any differential input interface standard being used in order to prevent instability when there is no input signal. table 2. pin characteristics (t a = +25c, f = 1.0mhz) ) note: this parameter is measured at characterization but not tested. number name type description 1, 12, 22 gnd power power supply return for all power. 2pd input lvttl power-down control. shuts off entire chip. if low, the device goes into low power mode. inputs and outputs are disabled. both qx and qx outputs will pull to v dd . set high for normal operation. (3) 3 reserved reserved reserved pin. 4, 9, 16, 21 v dd power power supply for the device core and inputs. 5, 7, 18, 20 q1 , q2 , q4 , q3 output lvds complementary differential clock outputs. 6, 8, 17, 19 q1, q2, q4, q3 output lvds differential clock outputs. 10 sel input lvttl reference clock se lect. when low, selects a2 and a2 . when high, selects a1 and a1 . 11 g input lvttl gate control for differ ential outputs q1 and q1 through q4 and q4 . when g is low, the differential outputs are active. when g is high, the differential outputs are asynchronously driven to the level designated by gl (2) . 13, 24 a1, a2 input adjustable (1, 4) clock input. a [1:2] is the "true" side of the differential clock input. 14, 23 a 1 , a 2 input adjustable (1, 4) complementary clock inputs. a[1:2] is the complementary side of a[1:2] . for lvttl single-ended operation, a[1:2] should be set to the desired toggle voltage for a[1:2]: 3.3v lvttl v ref = 1650mv 2.5v lvttl v ref = 1250mv 15 gl input lvttl specifies output disable level. if high, qx outputs disable high and qx outputs disable low. if low, qx outputs disable low and qx outputs disable high. symbol parameter test conditions minimum typical maximum units c in input capacitance 3pf
idt5t9304 revision a january 21, 2010 4 ?2010 integrated device technology, inc. idt5t9304 data sheet 2.5v lvds, 1:4 clock buffer terabuffer? function tables table 3a. gate control output table table 3b. input selection table absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operati on of product at these conditions or an y conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating condit ions for extended periods may affect product reliability. recommended operating range control output outputs gl g q[1:4] q[1:4] 0 0 toggling toggling 01 low high 1 0 toggling toggling 11 high low selection sel pin inputs 0a2, a2 1a1, a1 item rating power supply voltage, v dd -0.5v to +3.6v input voltage, v i -0.5v to +3.6v output voltage, v o not to exceed 3.6v -0.5 to v dd +0.5v storage temperature, t stg -65 c to 150 c junction temperature, t j 150 c symbol description minimum typical maximum units t a ambient operating temperature 0 25 70 c v dd internal power supply voltage 2.3 2.5 2.7 v
idt5t9304 revision a january 21, 2010 5 ?2010 integrated device technology, inc. idt5t9304 data sheet 2.5v lvds, 1:4 clock buffer terabuffer? dc electrical characteristics table 4a. lvds power supply dc characteristics (1) , v dd = 2.5v0.2v, t a = 0c to 70c note 1. these power consumption characteristics are for all th e valid input interfaces and cover the worst case conditions. note 2. the true input is held low and the complementary input is held high. table 4b. lvcmos/lvttl dc characteristics (1) , v dd = 2.5v0.2v, t a = 0c to 70c note 1. see recommended operating range table. note 2. typical values are at v dd = 2.5v, +25c ambient. note 3. for a[1:2] single-ended operation, a [1:2] is tied to a dc reference voltage. table 4c. differential dc characteristics (1) , v dd = 2.5v0.2v, t a = 0c to 70c note 1. see recommended operating range table. note 2. typical values are at v dd = 2.5v, +25c ambient. note 3. v dif specifies the minimum input differential voltage (v tr - v cp ) required for switching where v tr is the "true" input level and v cp is the "complement" input level. the dc differential voltage must be maintained to guarantee retaining the existing high or low in put. the ac differential voltage must be achieved to guarantee switching to a new state. note 4. v cm specifies the maximum allowable range of (v tr + v cp ) /2. symbol parameter test conditions minimum typical (2) maximum units i ddq quiescent v dd power supply current v dd = max., all input clocks = low (2) ; output enabled 240 ma i tot total power v dd supply current v dd = 2.7v; f reference clock = 450mhz 250 ma i pd total power down supply current pd = low 5 ma symbol parameter test conditions minimum typical (2) maximum units i ih input high current v dd = 2.7v 5 a i il input low current v dd = 2.7v 5 a v ik clamp diode voltage v dd = 2.3v, i in = -18ma -0.7 -1.2 v v in dc input voltage -0.3 3.6 v v ih dc input high voltage 1.7 v v il dc input low voltage 0.7 v v thi dc input threshold crossing voltage v dd /2 v v ref single-ended reference voltage (3) 3.3v lvttl 1.65 v 2.5v lvttl 1.25 v symbol parameter test co nditions minimum typical (2) maximum units i ih input high current v dd = 2.7v 5 a i il input low current v dd = 2.7v 5 a v ik clamp diode voltage v dd = 2.3v, i in = -18ma -0.7 -1.2 v v in dc input voltage -0.3 3.6 v v dif dc differential voltage (3) 0.1 v v cm dc common mode input voltage (4) 0.05 v dd v
idt5t9304 revision a january 21, 2010 6 ?2010 integrated device technology, inc. idt5t9304 data sheet 2.5v lvds, 1:4 clock buffer terabuffer? table 4d. lvds dc characteristics (1) , v dd = 2.5v0.2v, t a = 0c to 70c note 1. see recommended operating range table. note 2. typical values are at v dd = 2.5v, +25c ambient. ac electrical characteristics table 5a. hstl differential input ac characteristics, v dd = 2.5v0.2v, t a = 0c to 70c note 1. the 1v peak-to-peak input pulse level is specified to allow consistent, repeatable result s in an automatic test equipme nt (ate) environment. this device meets the v dif (ac) specification under actual use conditions. note 2. a 750mv crossing point level is specified to allow cons istent, repeatable results in an automatic test equipment (ate) environment. this device meets the v x specification under actual use conditions. note 3. in all cases, input waveform timing is marked at the differential cross-point of the input signals. note 4. the input signal edge rate of 2v/ns or greater is to be maintained in the 20% to 80% range of the input waveform. table 5b. ehstl ac differential input characteristics, v dd = 2.5v0.2v, t a = 0c to 70c note 1. the 1v peak-to-peak input pulse level is specified to allow consistent, repeatable result s in an automatic test equipme nt (ate) environment. this device meets the v dif (ac) specification under actual use conditions. note 2. a 900mv crossing point level is specified to allow cons istent, repeatable results in an automatic test equipment (ate) environment. this device meets the v x specification under actual use conditions. note 3. in all cases, input waveform timing is marked at the differential cross-point of the input signals. note 4. the input signal edge rate of 2v/ns or greater is to be maintained in the 20% to 80% range of the input waveform. symbol parameter test conditions minimum typical (2) maximum units v ot(+) differential output voltage for the true binary state 247 454 mv v ot(?) differential output voltage for the false binary state 247 454 mv ? v ot change in v ot between complementary output states 50 mv v os output common mode voltage (offset voltage) 1.125 1.2 1.375 v ? v os change in v os between complementary output states 50 mv i os outputs short circuit current v out+ and v out? = 0v 12 24 ma i osd differential outputs sh ort circuit current v out+ = v out? 612ma symbol parameter value units v dif input signal swing (1) 1v v x differential input signal crossing point (2) 750 mv d h duty cycle 50 % v thi input timing measurement reference level (3) crossing point v t r / t f input signal edge rate (4) 2v/ns symbol parameter value units v dif input signal swing (1) 1v v x differential input signal crossing point (2) 900 mv d h duty cycle 50 % v thi input timing measurement reference level (3) crossing point v t r / t f input signal edge rate (4) 2v/ns
idt5t9304 revision a january 21, 2010 7 ?2010 integrated device technology, inc. idt5t9304 data sheet 2.5v lvds, 1:4 clock buffer terabuffer? table 5c. lvepecl (2.5v) and lvpecl (3.3v) differential inpu t ac characteristics, v dd = 2.5v0.2v, t a = 0c to 70c note 1. the 732mv peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equi pment (ate) environment. this device meets the v dif (ac) specification under actual use conditions. note 2. a 1082mv lvepecl (2.5v) and 1880mv lvpecl (3.3v) crossi ng point level is specified to allow consistent, repeatable resu lts in an automatic test equipment (ate) environment. this device meets the v x specification under actual use conditions. note 3. in all cases, input waveform timing is marked at the differential cross-point of the input signals. note 4. the input signal edge rate of 2v/ns or greater is to be maintained in the 20% to 80% range of the input waveform. table 5d. lvds differential input ac characteristics, t a = 0c to 70c note 1. the 400mv peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equi pment (ate) environment. this device meets the v dif (ac) specification under actual use conditions. note 2. a 1.2v crossing point level is specified to allow consis tent, repeatable results in an automatic test equipment (ate) e nvironment. this device meets the v x specification under actual use conditions. note 3. in all cases, input waveform timing is marked at the differential cross-point of the input signals. note 4. the input signal edge rate of 2v/ns or greater is to be maintained in the 20% to 80% range of the input waveform. table 5e. ac differential input characteristics (1) , v dd = 2.5v0.2v, t a = 0c to 70c note 1. the output will not change state unt il the inputs have crossed and the minimum differential voltage range defined by v dif has been met or exceeded. note 2. v dif specifies the minimum input voltage (v tr ? v cp ) required for switching where v tr is the ?true? input level and v cp is the ?complement? input level. the ac diff erential voltage must be achieved to guarantee switching to a new state. note 3. v cm specified the maximum allowable range of (v tr + v cp ) /2. symbol parameter maximum units v dif input signal swing (1) 732 mv v x differential input cross point voltage (2) lvepecl 1082 mv lvpecl 1880 mv d h duty cycle 50 % v thi input timing measurement reference level (3) crossing point v t r / t f input signal edge rate (4) 2v/ns symbol parameter maximum units v dif input signal swing (1) 400 mv v x differential input cross point voltage (2) 1.2 v d h duty cycle 50 % v thi input timing measurem ent reference level (3) crossing point v t r / t f input signal edge rate (4) 2v/ns symbol parameter minimum typical maximum units v dif ac differential voltage (2) 0.1 3.6 v v x differential input cross point voltage 0.05 v dd v v cm common mode input voltage range (3) 0.05 v dd v v in input voltage -0.3 3.6 v
idt5t9304 revision a january 21, 2010 8 ?2010 integrated device technology, inc. idt5t9304 data sheet 2.5v lvds, 1:4 clock buffer terabuffer? table 5f. ac characteristics (1,5) , v dd = 2.5v0.2v, t a = 0c to 70c note. electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. note 1. ac propagation measurem ents should not be taken within the first 100 cycles of startup. note 2. skew measured between crosspoint of all differential output pairs under identical input and output interfaces, transiti ons and load conditions on any one device. note 3. skew measured is the difference between propagation delay times tp hl and tp lh of any differential output pair under identical input and output interfaces, transitions and load conditions on any one device. note 4. skew measured is the magnitude of the difference in propagation times between any singl e differential output pair of tw o devices, given identical transitions and load conditions at identical v dd levels and temperature. note 5. all parameters are te sted with a 50% input duty cycle. note 6. guaranteed by design but not production tested. symbol parameter test conditions minimum typical maximum units t sk(o) same device output pin-to-pin skew (2) 50 ps t sk(p) pulse skew (3) 125 ps t sk(pp) part-to-part skew (4) 300 ps tp lh propagation delay, low-to-high a crosspoint to qn, qn crosspoint 1.25 1.75 ns tp hl propagation delay, high-to-low 1.25 1.75 ns fo frequency range (6) 450 mhz t pge output gate enable crossing vthi-to-qn/qn crosspoint 3.5 ns t pgd output gate enable crossing vthi-to-qn/qn crosspoint driven to designated level 3.5 ns t pwrdn pd crossing v thi -to-qn = v dd , qn = v dd 100 s t pwrup output gate disable crossing v thi to qn/qn driven to designated level 100 s t r / t f output rise/fall time (6) 20% to 80% 125 600 ps
idt5t9304 revision a january 21, 2010 9 ?2010 integrated device technology, inc. idt5t9304 data sheet 2.5v lvds, 1:4 clock buffer terabuffer? differential ac timing waveforms output propagation and skew waveforms note 1: pulse skew is calculated using the following expression: t sk(p) = | tp hl ? tp lh | note that the tp hl and tp lh shown above ae not valid measurements for this calculat ion because they are not taken from the same pulse. note 2: ac propagation measurements should not be taken within the firs t 100 cycles of startup. differential gate disabled/endable showing runt pulse generation note 1: as shown, it is possible to generate runt pulses on gat e disable and enable of the outputs. it is the user?s responsibi lity to time the g signal to avoid this problem. t plh t phl t sk(o) t sk(o) qn - qn qm - qm + v dif v dif = 0 - v dif + v dif v dif = 0 - v dif a [1:2] - a [1:2] + v dif v dif = 0 - v dif 1/fo t plh gl g qn - qn t pgd t pge v ih v thi v il v ih v thi v il + v dif v dif = 0 - v dif a [1:2] - a [1:2] + v dif v dif = 0 - v dif
idt5t9304 revision a january 21, 2010 10 ?2010 integrated device technology, inc. idt5t9304 data sheet 2.5v lvds, 1:4 clock buffer terabuffer? power down timing note 1: it is recommended that outputs be disabled before ente ring power-down mode. it is also recommended that the outputs rem ain disabled until the device completes power-up after asserting pd . note 2: the power down timing diagram assumes that gl is high. note 3: it should be noted that during power-down mode, the outputs are both pulled to v dd . in the power down timing diagram this is shown when qn/qn goes to v dif = 0. a 1 - a 1 g v thi v ih v il qn - qn +v dif v dif =0 -v dif +v dif v dif =0 -v dif +v dif v dif =0 -v dif pd a 2 - a 2 v thi v ih v il
idt5t9304 revision a january 21, 2010 11 ?2010 integrated device technology, inc. idt5t9304 data sheet 2.5v lvds, 1:4 clock buffer terabuffer? test circuit for differential input table 6a. differential input test conditions symbol v dd = 2.5v 0.2v unit v thi crossing of a and a v v dd /2 d.u.t. a a pulse generator ~50 ? transmission line ~50 ? transmission line v in v in -v dd /2 scope 50 ? 50 ?
idt5t9304 revision a january 21, 2010 12 ?2010 integrated device technology, inc. idt5t9304 data sheet 2.5v lvds, 1:4 clock buffer terabuffer? test circuit for dc outputs and power down tests test circuit for propagation, skew , and gate enable/disable timing table 6b. differential input test conditions note 1: specifications only apply to ?n ormal operations? test condition. the t ia /e ia specification load is for reference only. note 2: the scope inputs are assumed to have a 2pf load to ground. t ia /e ia ? 644 specifies 5pf between the output pair. with c l = 8pf, this gives the test circuit appropriate 5pf equivalent load. symbol v dd = 2.5v 0.2v unit c l 0 (1) pf 8 (1,2) pf r l 50 ? v dd d.u.t. a a qn qn pulse generator r l r l v os v od v dd /2 d.u.t. a a qn qn pulse generator 50 ? 50 ? z = 50 ? z = 50 ? scope c l -v dd /2 c l
idt5t9304 revision a january 21, 2010 13 ?2010 integrated device technology, inc. idt5t9304 data sheet 2.5v lvds, 1:4 clock buffer terabuffer? package outline and package dimensions package outline - g suffix for 24 lead tssop table 7. package dimensions reference document: jedec publication 95, mo-153 all dimensions in millimeters symbol minimum maximum n 24 a 1.20 a1 0.5 0.15 a2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 d 7.70 7.90 e 6.40 basic e1 4.30 4.50 e 0.65 basic l 0.45 0.75 0 8 aaa 0.10
idt5t9304 revision a january 21, 2010 14 ?2010 integrated device technology, inc. idt5t9304 data sheet 2.5v lvds, 1:4 clock buffer terabuffer? ordering information table 8. ordering information idt xxxxx package device type 5t9304 2.5v lvds 1:4 glitchless clock buffer terabuffer ii thin shrink small outline package tssop - green pg pgg xx process x 0 c to +70 c (commercial) while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this produc t is intended for use in normal commercial applications. any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves t he right to change any circuitry or specifications without noti ce. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments.
idt5t9304 data sheet 2.5v lvds, 1:4 clock buffer terabuffer? disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the ri ght to modify the products and/or specif ications described herein at any time and at idt? s sole discretion. all information in this document, including descriptions of product features and performance, is s ubject to change without notice. performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. the informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt?s products for any partic ular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in life support systems or similar devices where the failure or malfunction of an idt p roduct can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own ri sk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered tr ademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2010. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056

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